IS43R16160D-5TL

ISSI
870-IS43R16160D-5TL
IS43R16160D-5TL

制造商：

说明：
动态随机存取存储器 256M (16Mx16) 200MHz 2.5v DDR S动态随机存取存储器

数据表:
ECAD模型:
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了解ISSI IS43R16160D-5TL详情

供货情况

库存：
无库存
生产周期：
最少： 1   倍数： 1
单价:
¥-.--
总价:
¥-.--
预估关税:

定价 (含13% 增值税)

数量 单价
总价
¥41.0303 ¥41.03
¥38.2957 ¥382.96
¥37.1431 ¥928.58
¥36.2278 ¥1,811.39
¥35.4029 ¥3,823.51
¥34.1599 ¥7,378.54
¥33.335 ¥18,000.90
¥32.5101 ¥35,110.91
¥31.6852 ¥82,128.04

可能的更换

ISSI IS43R16160F-5TL
ISSI
动态随机存取存储器 256M, 2.5V, DDR, 16Mx16, 166MHz
与当前部分进行比较

产品属性 属性值 选择属性
ISSI
产品种类: 动态随机存取存储器
RoHS:  
SDRAM - DDR
256 Mbit
16 bit
200 MHz
TSOP-II-66
16 M x 16
5 ns
2.3 V
2.7 V
0 C
+ 70 C
IS43R16160D
Tray
商标: ISSI
组装国: Not Available
扩散国家: Not Available
原产国: CN
湿度敏感性: Yes
安装风格: SMD/SMT
产品类型: DRAM
工厂包装数量: 108
子类别: Memory & Data Storage
电源电流—最大值: 330 mA
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已选择的属性: 0

数据表

Models

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CNHTS:
8542319090
USHTS:
8542320024
JPHTS:
854232021
KRHTS:
8542321010
MXHTS:
8542320201
ECCN:
EAR99

IS43R32800D 8Mx32 256-Mbit DDR SDRAM

ISSI IS43R32800D 8Mx32 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64MB to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages.

DDR SDRAM

ISSI 512-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence, and CAS latency enable further advantages. The device is available in 8-bit, 16-bit, and 32-bit data word sizes. Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. ISSI 512-Mbit DDR SDRAM commands are registered on the positive edges of CLK.

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